[Xen-changelog] The PAE guest can run on SMP 64-bit Xen0 now.

[Xen patchbot -unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User kaf24@xxxxxxxxxxxxxxxxxxxx
# Node ID 3219aa25ad46dc327fc5abf7b87e39050be5334a
# Parent  f55d6c299c7e2003fd97f1c7263f9f5195c0dca0
The PAE guest can run on SMP 64-bit Xen0 now.

Optimize the save/restore action for EFER MSR during the context switch.

Signed-off-by: Jun Nakajima jun.nakajima@xxxxxxxxx
Signed-off-by: Xiaohui Xin xiaohui.xin@xxxxxxxxx
Signed-off-by: Yunhong Jiang <yunhong.jiang@xxxxxxxxx>

diff -r f55d6c299c7e -r 3219aa25ad46 xen/arch/x86/hvm/vmx/vmx.c
--- a/xen/arch/x86/hvm/vmx/vmx.c        Wed Mar  8 10:51:17 2006
+++ b/xen/arch/x86/hvm/vmx/vmx.c        Wed Mar  8 10:53:39 2006
@@ -223,6 +223,11 @@
 
     switch (regs->ecx){
     case MSR_EFER:
+        /* offending reserved bit will cause #GP */
+        if ( msr_content &
+                ~( EFER_LME | EFER_LMA | EFER_NX | EFER_SCE ) )
+             vmx_inject_exception(vc, TRAP_gp_fault, 0);
+
         if ((msr_content & EFER_LME) ^
             test_bit(VMX_CPU_STATE_LME_ENABLED,
                      &vc->arch.hvm_vmx.cpu_state)){
@@ -236,18 +241,9 @@
         if (msr_content & EFER_LME)
             set_bit(VMX_CPU_STATE_LME_ENABLED,
                     &vc->arch.hvm_vmx.cpu_state);
-        /* No update for LME/LMA since it have no effect */
+
         msr->msr_items[VMX_INDEX_MSR_EFER] =
             msr_content;
-        if (msr_content & ~(EFER_LME | EFER_LMA)){
-            msr->msr_items[VMX_INDEX_MSR_EFER] = msr_content;
-            if (!test_bit(VMX_INDEX_MSR_EFER, &msr->flags)){
-                rdmsrl(MSR_EFER,
-                       host_state->msr_items[VMX_INDEX_MSR_EFER]);
-                set_bit(VMX_INDEX_MSR_EFER, &host_state->flags);
-                set_bit(VMX_INDEX_MSR_EFER, &msr->flags);
-            }
-        }
         break;
 
     case MSR_FS_BASE:
diff -r f55d6c299c7e -r 3219aa25ad46 xen/arch/x86/shadow.c
--- a/xen/arch/x86/shadow.c     Wed Mar  8 10:51:17 2006
+++ b/xen/arch/x86/shadow.c     Wed Mar  8 10:53:39 2006
@@ -3583,6 +3583,11 @@
 
     ASSERT( d->arch.ops->guest_paging_levels >= PAGING_L3 );
 
+#if CONFIG_PAGING_LEVELS >= 4
+    if ( (error_code & (ERROR_I | ERROR_P)) == (ERROR_I | ERROR_P) )
+        return 1;
+#endif
+
 #if CONFIG_PAGING_LEVELS == 4
     if ( d->arch.ops->guest_paging_levels == PAGING_L4 ) 
     {
diff -r f55d6c299c7e -r 3219aa25ad46 xen/include/asm-x86/shadow_64.h
--- a/xen/include/asm-x86/shadow_64.h   Wed Mar  8 10:51:17 2006
+++ b/xen/include/asm-x86/shadow_64.h   Wed Mar  8 10:53:39 2006
@@ -51,8 +51,11 @@
 #define READ_FAULT  0
 #define WRITE_FAULT 1
 
-#define ERROR_W    2
+#define ERROR_P     1
+#define ERROR_W     2
 #define ERROR_U     4
+#define ERROR_I     (1 << 4)
+
 #define X86_64_SHADOW_DEBUG 0
 
 #if X86_64_SHADOW_DEBUG

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