[Xen-changelog] Fix printing of u64 value 'msr_content' to use PRIx64 format.

[Xen patchbot -unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User kaf24@xxxxxxxxxxxxxxxxxxxx
# Node ID 7edd64c8bb36c9d0c30f3e7a5a79f75501f2e280
# Parent  34b7dd72aa55004df1f288f90b049b2522d8b3a0
Fix printing of u64 value 'msr_content' to use PRIx64 format.

Signed-off-by: Keir Fraser <keir@xxxxxxxxxxxxx>

diff -r 34b7dd72aa55 -r 7edd64c8bb36 xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c        Thu Mar  2 02:21:38 2006
+++ b/xen/arch/x86/hvm/svm/svm.c        Thu Mar  2 09:59:34 2006
@@ -298,13 +298,8 @@
         return 0;
     }
 
-#ifdef __x86_64__
-    HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %lx\n", 
+    HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %"PRIx64"\n", 
             msr_content);
-#else
-    HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %llx\n", 
-            msr_content);
-#endif
 
     regs->eax = msr_content & 0xffffffff;
     regs->edx = msr_content >> 32;
@@ -317,13 +312,9 @@
     struct vcpu *vc = current;
     struct vmcb_struct *vmcb = vc->arch.hvm_svm.vmcb;
 
-#ifdef __x86_64__
-    HVM_DBG_LOG(DBG_LEVEL_1, "mode_do_msr_write msr %lx msr_content %lx\n", 
-                regs->ecx, msr_content);
-#else
-    HVM_DBG_LOG(DBG_LEVEL_1, "mode_do_msr_write msr %x msr_content %llx\n", 
-                regs->ecx, msr_content);
-#endif
+    HVM_DBG_LOG(DBG_LEVEL_1, "mode_do_msr_write msr %lx "
+                "msr_content %"PRIx64"\n", 
+                (unsigned long)regs->ecx, msr_content);
 
     switch (regs->ecx)
     {
diff -r 34b7dd72aa55 -r 7edd64c8bb36 xen/arch/x86/hvm/vmx/vmx.c
--- a/xen/arch/x86/hvm/vmx/vmx.c        Thu Mar  2 02:21:38 2006
+++ b/xen/arch/x86/hvm/vmx/vmx.c        Thu Mar  2 09:59:34 2006
@@ -172,7 +172,7 @@
     switch(regs->ecx){
     case MSR_EFER:
         msr_content = msr->msr_items[VMX_INDEX_MSR_EFER];
-        HVM_DBG_LOG(DBG_LEVEL_2, "EFER msr_content %llx\n", (unsigned long 
long)msr_content);
+        HVM_DBG_LOG(DBG_LEVEL_2, "EFER msr_content %"PRIx64"\n", msr_content);
         if (test_bit(VMX_CPU_STATE_LME_ENABLED,
                      &vc->arch.hvm_vmx.cpu_state))
             msr_content |= 1 << _EFER_LME;
@@ -202,7 +202,8 @@
     default:
         return 0;
     }
-    HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %lx\n", 
msr_content);
+    HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %"PRIx64"\n",
+                msr_content);
     regs->eax = msr_content & 0xffffffff;
     regs->edx = msr_content >> 32;
     return 1;
@@ -216,8 +217,9 @@
     struct vmx_msr_state * host_state =
         &percpu_msr[smp_processor_id()];
 
-    HVM_DBG_LOG(DBG_LEVEL_1, " mode_do_msr_write msr %lx msr_content %lx\n",
-                regs->ecx, msr_content);
+    HVM_DBG_LOG(DBG_LEVEL_1, " mode_do_msr_write msr %lx "
+                "msr_content %"PRIx64"\n",
+                (unsigned long)regs->ecx, msr_content);
 
     switch (regs->ecx){
     case MSR_EFER:

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